This invention relates to an improved insulated gate field effect transistor and more particularly to an improved insulated gate field effect transistor provided with a novel drain region that promotes current flow deeper within the channel region of the device.
Field effect transistors are well known in the art and are comprised of a conductive gate electrode spaced from the surface of a suitably doped semiconductor body of a first conductivity type by a thin dielectric material. Source and drain electrodes are defined by spaced low resistance regions of opposite conductivity type in the semiconductor body. An electric field, usually generated by the metallic or conductive gate electrode, modulates the carrier density along the conduction channel between the source and drain electrodes.
The development of semiconductor devices, and the field effect transistor devices in particular, has the objective of improving performance by increasing the density, reducing capacitance, and increasing the sensitivity and the speed of operation. In increasing density, the channel region was shortened, which resulted in greater packing density and faster response. However, as the channel length was reduced, constraints were placed on the operating voltage of the device. Avalanche multiplication voltage of short N-channel insulated gate field effect transistor devices proved to be quite low. For a given operating voltage, this limits the minimum channel length of N-channel devices, and vice versa, a given minimum channel length limits the operating voltage. For a given FET having a short channel length, the electric field near the drain region is very high. When the voltage between the source and drain is increased, avalanching occurs first adjacent to the drain region near the surface of the device. Electrons and holes are generated by the avalanching phenomenon with a portion of the electrons being lodged in the dielectric layer between the gate and the body. This results in a negative charge which is permanent in nature that materially affects the threshold voltage of the device. Thus, as the channel length of the field effect transistor becomes shorter, the allowable operating voltage between the source and drain becomes smaller. The same situation exists with respect to P-channel devices but to a lesser extent.
In addition to the avalanching situation, electrons can become trapped in the gate dielectric to adversely affect the threshold stability of an FET during pre-avalanche operation. In normal operation of an FET, a voltage is impressed across the source and drain. This voltage difference creates an electric field which will cause current or electron flow. In current flow through semiconductor material, some energetic electrons are present which have sufficient energy to overcome the barrier presented by the semi-conductor-gate dielectric interface barrier. Electrons that escape into the dielectric can become trapped in the dielectric. If the dielectric has an Si.sub.3 N.sub.4 --SiO.sub.2 interface, the trapping probability is several orders of magnitude greater than with a simple SiO.sub.2 gate dielectric. Trapped electrons result in a permanent charge in the dielectric which alters the threshold voltage of the device, as well as other electrical characteristics. The shorter the channel length, the greater the electric field that is generated. The greater the field, the greater is the probability of an electron achieving sufficient energy to traverse the barrier. Since the trend in FET design is to smaller devices with shorter channel lengths, it is apparent that the deterioration of threshold stability due to trapped electrons in the gate dielectric is a significant and possibly limiting consideration. The same basic situation exists in a P-channel device as in the aforedescribed N-channel device but to a lesser extent.